The circuit topology of oscillators generally used for generating a square wave is based on the constant-current charging of one or more capacitors between two levels of voltage. The oscillating frequency of this type of oscillator is set by the time that the capacitor takes to charge from one level of voltage to the other. That is, it is given by the ratio between the charging capacity of the capacitor and the charging current.
For these types of oscillators there are various methods for controlling the charging or discharging of the capacitor; amongst the most common are the method of controlling the transistor threshold voltage and the method of controlling through differential comparators.
With the first method a terminal of the capacitor is connected to the gate terminal of a MOS transistor whose task is to block the charging of the capacitor when it is on and to reactivate it when it is off. This control method is simple but it is strongly dependent on the temperature and on the process variables.
With the second method the output of a differential comparator that compares the voltage on the capacitor with a reference voltage is used to activate or deactivate the charging of the capacitor. This type of control is more complex but it is more stable. Further, its consumption increases with the frequency given that the correct functioning depends on the speed of response of the differential comparator.
FIG. 1 shows a constant-charge oscillator with a control device based on differential comparators. The oscillator comprises two capacitors C1 and C2 charged by a current I through two current mirrors QP1-QP3 and QP2-QP3 that are connected to the supply voltage Vcc. The first capacitor C1 has a terminal connected to ground and the other terminal connected to the non-inverting terminal of a first differential comparator Comp1 that has its inverting terminal connected to a reference voltage Vref1. The second capacitor C2 has a terminal connected to ground and the other terminal connected to the non-inverting terminal of a second differential comparator Comp2 that has its inverting terminal connected to the reference voltage Vref1. The outputs P1 and P2 of the comparators Comp1 and Comp2 respectively constitute the set input S and reset input R of a set-reset flip-flop FF1 whose outputs Q and Qneg are the drive voltages of two MOS transistors QN1 and QN2 having their drain terminals connected to the terminal of the capacitor C1 and the terminal of the capacitor C2, respectively. The voltage levels are ground and the reference voltage Vref1, and the half-period is given by the time taken by the voltage at the terminals of the capacitors C1 and C2 to go from ground to the reference voltage Vref1.
The comparators COMP1 and COMP2 generate the signals needed for controlling the charging and discharging of the capacitors C1 and C2. When the outputs of the flip-flop FF1 are Q=0 and Qneg=1, the transistor QN1 is off. In this way the capacitor C1 can charge itself with the current I supplied by the mirror QP1-QP3 while the transistor QN2 is on keeping the second capacitor C2 discharged and the voltage on the non-inverting terminal of the second comparator Comp2 at ground. The first capacitor C1 will charge until the voltage on the non-inverting terminal of the first comparator Comp1 reaches the reference voltage Vref1, making the output of the first comparator Comp1 switch from 0 to 1 and setting the outputs of the flip-flop FF1 at Q=1 and Qneg=0. In this way the transistor QN1 turns on rapidly discharging the first capacitor C1 and the transistor QN2 turns off enabling the charging of the second capacitor C2 with the current I supplied by the mirror QP2-QP3. The second capacitor C2 will charge until the voltage on the non-inverting terminal of the first comparator Comp1 reaches the reference voltage Vref1, making the first comparator COMP1 switch and bringing back the flip-flop FF1 to its starting state. In this way the charging and discharging cycle of the capacitors C1 and C2 is alternated. If the transistor QP1 and the first capacitor C1 are equal respectively to the transistor QP2 and to the second capacitor C2, a square wave with a duty-cycle of 50% will be generated at the output and supplied to the flip-flop FF1.
A serious limitation in frequency in the use of this type of oscillator is the switching speed of the comparators COMP1 and COMP2. FIG. 2 shows how the voltage Vcp evolves at the terminals of the two capacitors C1 and C2; actually the comparators do not switch when the voltage in the capacitors reaches the reference voltage Vref1 but a period of time Δt after due to the delay of the comparator. At high frequencies, when the period of time Δt is not negligible compared to the period of oscillation T, the working frequency of the oscillator cannot be set only by the current-capacity ratio in the capacitors but there must also be considered a variable Δt with the working conditions. In addition, at high frequency, a high speed of charging or discharging enables the transformation of the period of time Δt into a high variation of voltage ΔV, compromising the functioning of the oscillator at low supply voltages.